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Posted: Wednesday, February 7, 2018 6:16 PM

Component Design Engineers are responsible for the design and development of electronic components.

Responsibilities may include:

  • The design of chip layout circuit design, circuit checking, device evaluation and characterization, documentation of specifications, prototype construction and checkout, modification and evaluation of semiconductor devices and components, performing developmental and/or test work, reviewing product requirements and logic diagrams, planning and organizing design projects or phases of design projects.
  • Responds to customer/client requests or events as they occur. Develops solutions to problems utilizing formal education and judgement.


Minimum Qualifications: You must possess a minimum of a Bachelor of Science degree in Electrical Engineering or Computer Engineering Computer Science with at least 15 years of experience in IC Design, ASIC or Computer Aided Design CAD, or a Masters Degree in Electrical Engineering or Computer Engineering Computer Science with at least 7 years of experience in IC Design, ASIC or Computer Aided Design CAD. Experience with complex Tapeout flows, waivers, tapeout checklists and in-depth QA/Regression- Excellent programming skills: Unix, Perl, Python, Skill, Tcl, C/C++ or other Practical experience and solid track record with data management software is expected DesignSync, Mercurial, Git/Gatekeeper, etc.. Solid track record with Cadence, Synopsys and/or Mentor tools is expected- Solid experience with Intel internal tools and flows would be a plus DTS, ICF Demonstrate expertise with various Electronic Design Automation EDA software, flows and architecture Demonstrate a solid understanding of Integrated Circuit IC, ASIC simulation tools and related methodologies Demonstrate experience in front-to-back digital or analog flows RTL to GDS expert, or SPICE to GDS expert - Demonstrate experience with multiple CAD flows: frontend, backend, custom, digital, collateral PDK, FDK- Demonstrate experience in CMOS Design, ASIC Design, VLSI and Device Physics Demonstrate experience to interface with engineers, senior managers and stakeholders by providing schedule updates and roadmap plans- Demonstrate experience to mentor, coach and lead small groups of junior engineers working across Intel sites - DA/CAD Management experience would be a plus Experience with Cadence DFII environment such as Schematic Composer and/or Virtuoso Layout Editor Experience with Synopsys Digital tools such as Design Compiler DC, IC Compiler ICC, ICC2, Primetime PT and other Logic Design Automation tools or scripts Demonstrate understanding of RTL Synthesis, APR, Timing Closure Physical Design and Verification Demonstrate experience with Mentor Graphics software such as Calibre for DRC/LVS or Star-RCXT for Parasitic Extraction Additional qualifications include:- Prior experience with Intel Labs, Intel startups or with Intel Non-Volatile Memory Solutions Group NSG, Flash would be a plus Familiarity with external Foundries would be a plus TSMC or other Excellent communication skills and presentation skills Team player and self-motivated technical leader aligned with Intel values

Inside this Business Group

Non-Volatile Solutions Memory Group: The Non-Volatile Memory Solutions Group is a worldwide organization that delivers NAND flash memory products for use in Solid State Drives (SSDs), portable memory storage devices, digital camera memory cards, and other devices. The group is responsible for NVM technology design and development, complete Solid State Drive (SSD) system hardware and firmware development, as well as wafer and SSD manufacturing.

Other Locations

US, California, Santa Clara

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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• Location: Sacramento

• Post ID: 20732607 sacramento is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2018