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Posted: Wednesday, February 7, 2018 5:55 PM

Candidate will be a senior functional lead responsible for entire backend design implementation and optimization function which involves developing and supporting tools, flows and methodologies for chip design for a wide range of IPs on multiple manufacturing technology nodes.

He/She will closely work with internal stakeholders, internal customers and industry EDA partners to define, develop and deploy leading-edge chip design solutions to achieve best-in-class Hard-IP delivery in terms of frequency, power and die area with minimal Time to Market (TTM) development of these IPs.

He/She will be expected to define, lead and coordinate the deliverables of cross-geo technical contributors in multiple disciplines and manage stakeholder requirements to ensure the delivery of a complete design solution that meets all the requirements of the chip design team.


Minimum Qualifications:

  • Candidate should possess Master of Science MS degree or equivalent in Electrical/Computer Engineering with 10 or more years of relevant, hands-on work experience.
  • Extensive experience in the usage of EDA tools, typical design implementation tradeoffs and optimization strategies acquired through the implementation of RLS RTL to Layout Synthesis designs through all phases of the design cycle from technology readiness, floorplanning, design execution, design integration to chip finishing.
  • Possess a good understanding of diverse IP Intellectual Property design styles/requirements such as chipset, CPU, GPU, high speed designs and the corresponding tool/flow/methodology solutions and experience in delivering them as Hard IPs as part of the SOC System on a Chip design.
  • Extensive experience in creating, optimizing and supporting end-to-end chip design and analysis flows using industry-leading EDA solutions for logical/topographical synthesis, Automatic Place & Route P&R, Clock Mesh CTMesh implementation, ECO Engineering Change Order, Static Timing Analysis STA and timing convergence, Quality/formal equivalence verification, integration and sign-off.
  • Strong familiarity with VLSI CAD techniques/algorithms for low power design dynamic and leakage power reduction, gate sizing based optimizations and die size reduction.
  • Extensive understanding of tools and flows required to achieve the design rule requirements of leading-edge manufacturing technology nodes such as 22nm, 14nm and beyond.
  • Candidate should have demonstrated excellent communication and strategic planning skills as demonstrated through effective cross-site stakeholder management and functionally leading cross-geo engineering teams of individual technical contributors.

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel’s next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

Posting Statement. Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.

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• Location: Sacramento

• Post ID: 21870462 sacramento is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2018